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TeraScale is the codename for a family of graphics processing unit microarchitectures developed by ATI Technologies/AMD and their second microarchitecture implementing the unified shader model following ''Xenos''. TeraScale replaced the old fixed-pipeline microarchitectures and competed directly with Nvidia's first unified shader microarchitecture named Tesla.〔(【引用サイトリンク】title=Anatomy of AMD’s TeraScale Graphics Engine )〕 TeraScale was used in HD 2000 manufactured in 80 nm and 65 nm, HD 3000 manufactured in 65 nm and 55 nm, HD 4000 manufactured in 55 nm and 40 nm, HD 5000 and HD 6000 manufactured in 40 nm. TeraScale was also used in the AMD Accelerated Processing Units code-named "Brazos", "Llano", "Trinity" and "Richland". TeraScale is even found in some of the succeeding graphics cards brands. TeraScale is a VLIW SIMD architecture, while Tesla is a RISC SIMD architecture, similar to TeraScale's successor Graphics Core Next. TeraScale implements HyperZ.〔(【引用サイトリンク】title=Feature matrix of the free and open-source "Radeon" graphics device driver )〕 An LLVM code generator (i.e. a compiler back-end) is available for TeraScale, but it seems to be missing in LLVM's matrix.〔(Target-specific Implementation Notes: Target Feature Matrix ) // The LLVM Target-Independent Code Generator, LLVM site.〕 E.g. Mesa 3D makes use of it. == TeraScale 1 == At SIGGRAPH 08 in December 2008 AMD employee Mike Houston described some of the TeraScale microarchitecture.〔(【引用サイトリンク】title=Anatomy of AMD’s TeraScale microarchitecture )〕 At FOSDEM09 somebody presented a slide regarding the programming of open-source driver for the R600.〔http://www.vis.uni-stuttgart.de/~hopf/pub/Fosdem_2009_r600demo_Slides.pdf〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「TeraScale (microarchitecture)」の詳細全文を読む スポンサード リンク
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